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DS1384 watchdog timekeeping controller DS1384 062598 1/15 features ? keeps track of hundredths of seconds, seconds, min- utes, hours, days, date of the month, months, and years with leap year compensation valid up to 2100 ? watchdog timer restarts an outofcontrol processor ? alarm function schedules real-time related activities ? programmable interrupts and square wave outputs ? bytewide ramlike access ? 50 bytes of on board user ram ? greater than 10 years timekeeping and data retention in the absence of power with small lithium coin cells ? supports up to 128k x 8 of external static ram ? all timekeeping registers and on board ram are indi- vidually addressable via the address and data bus pin assignment a15 v bat1 we a13 a8 a9 a11 oe a10 ce oer intb /(intb) nc a14 a12 a7 a6 a5 a4 a3 a2 a1 1 11 33 23 12 22 44 34 gnd x1 x2 gnd a16 inta v v sqw pf0 v a0 dq0 dq1 dq2 gnd dq3 dq4 dq5 dq6 dq7 ceo cc cco bat2 pin description inta interrupt output a (open drain) intb (intb) interrupt output b (open drain) a0a16 address inputs dq0dq7 data input/output ce chip enable oe output enable we write enable v cc +5 volt input gnd ground nc no connection sqw square wave output x1, x2 32.768 khz crystal connections pfo power fail output ceo chip enable ram oer output enable ram v cco voltage out v bat1 +3 volt battery input v bat2 +3 volt battery input description the DS1384 watchdog timekeeping controller is a self-contained real time clock, alarm, watchdog timer, and interval timer which provides control of up to 128k x 8 of external low power cmos static ram in a 44pin quad flat pack package. an external crystal and battery are the only components required to maintain time of day and ram memory contents in the absence of pow- er. access to all rtc functions and the external ram is
DS1384 062598 2/15 the same as conventional bytewide sram. data is maintained in the watchdog timekeeper by intelligent control circuitry which detects the status of v cc and write protects both memory and timekeeping functions when v cc is out of tolerance. timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. the date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap year. the timekeeper operates in either 12 or 24hour format with an am/pm indicator. the watchdog internal timer provides watchdog alarm windows and interval timing between 0.01 seconds and 99.99 seconds. the real time alarm provides for preset times of up to one week. all of the rtc functions and the internal 50 bytes of ram reside in the lower 64 bytes of the attached ram memory map. the externally attached static ram is controlled by the DS1384 via the oer and ceo signals. automatic backup and write protection for an external sram is provided through the v cco , ceo and oer pins. the lithium energy source used to permanently power the real time clock is also used to retain ram data in the absence of v cc power through the v cco pin. the chip enable output to ram (ceo ) and the output enable to ram (oer ) are controlled during power transients to prevent data corruption. the DS1384 is a complete onechip solution in that an external crystal and battery are the only components required to maintain time of day memory status in the absence of power. signal descriptions v cc , gnd dc power inputs: dc operating voltage is provided to the device on these pins. v cc is the +5v input. v bat1 , v bat2 battery inputs for any standard 3volt lithium cell or other energy source. battery voltage must be held between 2.4 and 4 volts for proper operation. in the absence of power, the DS1384 will have a maximum load of 0.5 m a at 25 c. this should be added to the amount of current drawn from the external ram in standby mode at 25 c to size the external energy source. the DS1384 samples v bat1 and v bat2 and always selects the battery with the higher voltage. if only one battery is used, the unused battery input must be grounded. a16a0 address bus (inputs): the address bus inputs qualified by ce , oe , we , and v cc voltage are used to select the onchip 64 timekeeping/ram regis- ters within the memory map of the external sram con- trolled as nonvolatile storage. when the qualified address bus value is within the range of 00000h 0003fh, one of the internal registers will be selected and oer will remain inactive. when the value is outside of the range, oe will be passed through to oer . d7d0 data bus (bidirectional): when a qualified address from 00000h through 0003fh is presented to the device, data is passed to or from the onchip 64 timekeeping/ram registers via the data bus lines. data will be written on the rising edge of we when ce is active. if ce is active without we , data is read from the device and driven onto the data bus pins when oe is low. v cco switched dc power for sram (output): this pin will be connected to v cc when v cc voltage is above v so (the greater of v bat1 or v bat2 ). when v cc voltage falls below this level, v cco will be connected to the higher voltage battery pin. ceo ram chip enable (output; active low): when power is good the ce input will be passed through to ceo . if v cc is below v pf , ceo will remain at an inactive high level. oer ram output enable (output; active low): when power is good and the address value is not within the range of 00000h and 0003fh, and ce is active, the oe input will be passed through to oer . if these conditions are not met, oer will remain at an inactive high level. ce chip enable (input; active low): the chip enable signal must be asserted low during a bus cycle to access the onchip timekeeping ram registers, or to access the external ram via ceo . oe output enable (input; active low): the output enable signal identifies the time period when either the rtc or the external sram drives the bus with read data, provided that ce is valid with we disabled. when one of the 64 onchip registers is selected during a read cycle, the oe is the enable signal for the DS1384 output buffers and the data bus will be driven with read data. when the external ram is selected during a read cycle, the oe signal will be passed through to the oer pin so that read data will be driven by the external sram. we write enable (input; active low): the write enable signal identifies the time period during which data is writ- ten to either the onchip registers or to an external
DS1384 062598 3/15 sram location. when one of the onchip 64 registers is addressed, data will be written to the selected register on the rising edge of we . inta interrupt output a (output; active low): interrupt output a can be programmed as a time of day alarm or as a watchdog alarm (interrupt output b becomes the alternate function). in addition, inta can be pro- grammed to output either a pulse or a level. intb interrupt output b (output; active high or low): interrupt output b outputs the alarm (time of day or watchdog) that is not selected for inta . interrupt output b is programmable high or low. both inta and intb (intb) are open drain outputs. the two interrupts and the internal clock continue to run regardless of the level of v cc . however, it is important to insure that the pullup resistors used with the inter- rupt pins are never pulled up to a value which is greater than v cc + 0.3v. as v cc falls below approximately 3.0 volts, a power switching circuit turns the lithium energy source on the maintain the clock, and timer data functionality. it is also required to insure that during this time (battery backup mode), the voltage present at inta and intb (intb) does never exceed v bat . at all times the current on each should not exceed +2.1 ma or 1.0 ma. x1, x2 crystal inputs: connections for a standard 32.768 khz quartz crystal. when ordering, request a load capacitance or 6 pf. the internal oscillator circuitry is designed for operation with a crystal having a speci- fied load capacitance (c l ) of 6 pf. for more information on crystal selection and crystal layout considerations, please consult application note 58, acrystal considerations with dallas real time clockso. sqw square wave (output): this pin can be pro- grammed to output a 1024 hz square wave signal. when the signal is turned off, the pin is high z. pfo power fail signal (output; active low when v wp occurs): high state occurs t rec after powerup and v cc > 4.5 volts. address decoding the DS1384 accommodates 17 address lines which al- lows direct connection of up to 128k bytes of static ram. the lower 14 bytes of ram, regardless of the density used, will always contain the timekeeping, alarm, and watchdog registers. the 14 clock registers reside in the lower 14 ram locations without conflict by inhibiting the oer (output enable ram) signal during clock access. since the watchdog timekeeping chip ac- tually contains 64 registers (14 rtc and 50 user ram), the lower 64 bytes of any attached memory resides with- in the DS1384. however, the ram's physical location is transparent to the user and the memory map looks con- tinuous from the first clock address to the upper most at- tached ram address. operation read cycle the DS1384 executes a read cycle whenever we is inactive (high) and ce and oe are active (low). the unique address specified by the address inputs (a0a16) defines which of the onchip 64 rtc/ram or external sram locations is to be accessed. when the address value presented to the DS1384 is in the range of 00000h through 0003fh, one of the 64 on chip registers will be selected and valid data will be available to the eight data output drivers within t acc (access time) after the address input signal is stable, providing that the ce and oe access times are also satisfied. if they are not, then data access must be mea- sured from the latter occurring signal (ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than the address access time. when one of the onchip registers is selected for read, the oer signal will remain inactive throughout the read cycle. when the address value presented to the DS1384 is in the range of 00040h through 1ffffh, an external sram location will be selected. in this case the oe sig- nal will be passed to the oer pin, with the specified delay times of t aoel or t oerl . operation write cycle the DS1384 is in the write mode whenever the we (write enable) and ce (chip enable) signals are in the active (low) state after the address inputs are stable. the latter occurring falling edge of ce or we will deter- mine the start of the write cycle. the write cycle is termi- nated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery state (t wr ) before another cycle can be initiated. data must be valid on the data bus with sufficient data set up
DS1384 062598 4/15 (t ds ) and data hold time (t dh ) with respect to the earlier rising edge of ce or we . the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus has been enabled (ce and oe active), then we will disable the outputs in t wez from its falling edge. when the address value presented to the DS1384 dur- ing the write is in the range of 00000h through 0003fh, one of the 64 onchip registers will be selected and data will be written into the device. when the address value presented to the DS1384 dur- ing the write is in the range of 00040h through 1ffffh, an external sram location will be selected. data retention mode when v cci is within nominal limits (v cc > 4.5 volts) the DS1384 can be accessed as described above with read or write cycles. however, when v cc is below the power fail point, v pf , (point at which write protection occurs) the internal clock registers and external ram is blocked from access. this is accomplished internally by inhibit- ing access to the clock registers via the ce signal. at this time the power fail output signal (pfo ) is driven ac- tive and will remain active until v cc returns to nominal levels. external ram access is inhibited in a similar manner by forcing ceo to high level. this level is within 0.2 volts of the v cci input. ceo will remain at this level as long as v cci remains at an outoftolerance condi- tion. when v cci falls below the level of the battery (v bat1 or v bat2 ), power input is switched from the v cci pin to the v bat pin and the clock registers are main- tained from the attached battery supply. external ram is also powered by the v bat input when v cci is below v bat pin through the v cco pin. the v cco pin is capable of supplying 100 m a of current to the attached memory with less than 0.3 volts drop under this condition. on power up, when v cci returns to intolerance conditions, write protection continues for 150 ms by inhibiting ceo . the pfo signal also remains active during this time. the DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications which require added reliability or increased battery ca- pacity. when two batteries are used, the higher of the two is selected for use. a selected battery will remain as backup supply until it is significantly below the other. when the selected battery voltage falls below the alter- nate battery by about 0.6 volts, the alternate battery is selected and then becomes the backup supply. this switching occurs transparent to the user and continues until both batteries are exhausted. when only a single battery is required, both battery inputs can be con- nected together. however, a more effective method of using a single battery supply is to ground the unused battery input. when using a single battery, v bat1 is the preferred input. watchdog timekeeper registers the DS1384 watchdog timekeeper controller has 14 internal registers which are eight bits wide and contain all of the timekeeping, alarm, watchdog, control, and data information. the clock, calendar, alarm and watchdog registers are memory locations which con- tain external (user accessible) and internal copies of the data. the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see figure 1). the command register bits are af- fected by both internal and external functions. this reg- ister will be discussed later. the 50 bytes of ram regis- ters are accessed from the external address and data bus and reside or overlay external static ram. regis- ters 0, 1, 2, 4, 6, 8, 9 and a contain time of day and date information (see figure 2). time of day information is stored in bcd. registers 3, 5, and 7 contain the time of day alarm information. time of day alarm information is stored in bcd. register b is the command register and information in this register is binary. register c and d are the watchdog alarm registers and information which is stored in these two registers is in bcd. regis- ter 0000eh through register 0003fh are onchip user bytes and can be used to contain data at the user's dis- cretion.
DS1384 062598 5/15 DS1384 block diagram figure 1 command register update seconds thru years and check time of day alarm external registers, clock, calendar, time of day alarm internal counters internal counters external registers watchdog alarm divide by 4 swap pins power switch pf delay divide by 10 divide by 40.96 divide by 40.96 divide by 8 oscillator address decode and control data i/0 buffers jitter generator oscillator & prescaler quartz crystal d7d0 4096hz 32.788hz jitter generator vbat v cc 1024hz sqw x1 x2 100hz 100hz aavgo a0a16 ce oe we inta intb(intb) td int wd int aavgo internal registers a0a12 nv ram control pfo ceo oer 50 x 8 nv ram external registers hundredths of seconds
DS1384 062598 6/15 DS1384 watchdog timekeeper registers figure 2 esqw eosc 0 address bit 7 bit 0 range watchdog alarm registers command registers user registers clock, calendar, time of day alarm registers 1 2 3 4 5 6 7 8 9 a b c d e 0099 0059 0059 0059 0112+a/p 0023 0107 0107 0131 0112 0099 0099 0099 0112+a/p 0023 1ffff 0.1 seconds 0.01 seconds 0 10 seconds seconds 0 10 minutes minutes m 10 min alarm min alarm 0 12/24 10 a/p 10 hr hours m 12/24 10 a/p 10 hr hr alarm 00 0 0 0 days m 0 0 0 0 day alarm 0 0 10 date date 0 10 mo months 10 years years te ipsw ibh lo lvl pu wam tdm waf tdf 0.1 seconds 0.01 seconds 10 seconds seconds
DS1384 062598 7/15 time of day alarm mask bits figure 3 minutes hours days 1 0 alarm once per minute alarm when minutes match alarm when hours and minutes match alarm when hours, minutes, and days match 11 1 1 1 0 0 00 0 note: any other bit combinations of mask bit settings produce illogical operation. register time of day registers registers 0, 1, 2, 4, 6, 8, 9 and a contain time of day data in bcd. ten bits within these eight registers are not used and will always read zero regardless of how they are written. bits 6 and 7 in the months register (9) are binary bits. when set to logical zero, eosc (bit 7) enables the real time clock oscillator. this bit will normally be turned on by the user during device initialization. however, the os- cillator can be turned on and off as necessary by setting this bit to the appropriate level. bit 6 of this same byte controls the square wave output (pin 24). when set to logical zero, the square wave out- put pin will output a 1024 hz square wave signal. when set to logic one the square wave output pin is in a high impedance state. bit 6 of the hours register is defined as the 12 or 24hour select bit. when set to logic one, the 12hour format is selected. in the 12hour format, bit 5 is the am/ pm bit with logical one being pm. in the 24hour mode, bit 5 is the second 10hour bit (2023 hours). the time of day registers are updated every 0.01 seconds from the real time clock, except when the te bit (bit 7 of regis- ter b) is set low or the clock oscillator is not running. the preferred method of synchronizing data access to and from the watchdog timekeeper is to access the command register by doing a write cycle to address lo- cation 0b and setting the te bit (transfer enable bit) to a logic zero. this will freeze the external time of day regis- ters at the present recorded time allowing access to oc- cur without danger of simultaneous update. when the watch registers have been read or written a second write cycle to location 0b, setting the te bit to a logic one, will put the time of day registers back to being up- dated every 0.01 second. no time is lost in the real time clock because the internal copy of the time of day regis- ter buffers are continually incremented while the exter- nal memory registers are frozen. an alternate method of reading and writing the time of day registers is to ignore synchronization. however, any single read may give er- roneous data as the real time clock may be in the pro- cess of updating the external memory registers as data is being read. the internal copies of seconds through years are in- cremented and time of day alarm is checked during the period that hundredths of seconds reads 99 and are transferred to the external register when hundredths of seconds roll from 99 to 00. a way of making sure data is valid is to do multiple reads and compare. writing the registers can also produce erroneous results for the same reasons. a way of making sure that the write cycle has caused proper update is to do read verifies and re- execute the write cycle if data is not correct. while the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the proba- bility of an incorrect result is kept to a minimum due to the redundant structure of the watchdog timekeeper. time of day alarm registers registers 3, 5, and 7 contain the time of day alarm regis- ters. bits 3, 4, 5, and 6 of register 7 will always read zero regardless of how they are written. bit 7 of registers 3, 5, and 7 are mask bits (figure 3). when all of the mask bits are logical zero, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. an alarm will be generated every day when bit 7 of register 7 is set to a logical one. similarly, an alarm is generated every hour when bit 7 of registers 7
DS1384 062598 8/15 and 5 is set to a logical 1. when bit 7 of registers 7, 5, and 3 is set to a logical 1, an alarm will occur every min- ute when register 1 (seconds) rolls from 59 to 00. time of day alarm registers are written and read in the same format as the time of day registers. the time of day alarm flag and interrupt is always cleared when alarm registers are read or written. watchdog alarm registers registers c and d contain the time for the watchdog alarm. the two registers contain a time count from 00.01 to 99.99 seconds in bcd. the value written into the watchdog alarm registers can be written or read in any order. any access to register c or d will cause the watchdog alarm to reinitialize and clears the watchdog flag bit and the watchdog interrupt output. when a new value is entered or the watchdog registers are read, the watchdog timer will start counting down from the entered value to zero. when zero is reached, the watchdog interrupt output will go to the active state. the watchdog timer countdown is interrupted and re- initialized back to the entered value every time either of the registers are accessed. in this manner, controlled periodic accesses to the watchdog timer can prevent the watchdog alarm from ever going to an active level. if access does not occur, countdown alarm will be repet- itive. the watchdog alarm registers always read the entered value. the actual count down register is inter- nal and is not readable. writing registers c and d to zero will disable the watchdog alarm feature. command register address location 0bh is the command register where mask bits, control bits and flag bits reside. the opera- tion of each bit is as follows: te bit 7 transfer enable this bit when set to a logic 0 will disable the transfer of data between internal and ex- ternal clock registers. the contents in the external clock registers are now frozen and reads or writes will not be affected with updates. this bit must be set to a logic 1 to allow updates. ipsw bit 6 interrupt switch when set to a logic 1, inta is the time of day alarm and intb/(intb ) is the watchdog alarm. when set to logic 0, this bit reverses the output pins. inta is now the watchdog alarm output and intb/(intb ) is the time of day alarm output. ibh/lo bit 5 interrupt b sink or source current - when this bit is set to a logic 1 and v cc is applied, intb/(intb ) will source current (see dc characteristics i oh ). when this bit is set to a logic 0, intb will sink cur- rent (see dc characteristics i ol ). pu/lvl bit 4 interrupt pulse mode or level mode - this bit determines whether both interrupts will output a pulse or level signal. when set to a logic 0, inta and intb/(intb ) will be in the level mode. when this bit is set to a logic 1, the pulse mode is selected and inta will sink current for a minimum of 3 ms and then release. intb/(intb ) will either sink or source current, depend- ing on the condition of bit 5, for a minimum of 3 ms and then release. wam bit 3 watchdog alarm mask when this bit is set to a logic 0, the watchdog interrupt output will be acti- vated. the activated state is determined by bits 1,4,5, and 6 of the command register. when this bit is set to a logic 1, the watchdog interrupt output is deactivated. tdm bit 2 time of day alarm mask when this bit is set to a logic 0, the time of day alarm interrupt output will be activated. the activated state is determined by bits 0,4,5, and 6 of the command register. when this bit is set to a logic 1 , the time of day alarm interrupt out- put is deactivated. waf bit 1 watchdog alarm flag this bit is set to a logic 1 when a watchdog alarm interrupt occurs. this bit is read only. the bit is reset when any of the watchdog alarm regis- ters are accessed. when the interrupt is in the pulse mode (see bit 4 defini- tion), this flag will be in the logic 1 state only during the time the interrupt is active. tdf bit 0 time of day flag this is a read only bit. this bit is set to a logic 1 when a time of day alarm has occurred. the time the alarm occurred can be deter- mined by reading the time of day alarm registers. this bit is reset to a logic 0 state when any of the time of day alarm registers are accessed. when the interrupt is in the pulse mode (see bit 4 defini- tion), this flag will be in the logic 1 state only during the time the interrupt is active.
DS1384 062598 9/15 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 20 c to +70 c soldering temperature 260 c for 10 seconds *this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 logic 1 voltage all inputs v ih 2.2 v cc +0.3 v logic 0 voltage all inputs v il 0.3 0.8 v battery input voltage v bat 2.4 4.0 v dc electrical characteristics (0 c to 70 c; v cc = 5v 10%) parameter symbol min typ max units notes average v cc power supply current i cc1 7 15 ma 2, 3 ttl standby current (ce = v ih , ce2 = v il ) i cc2 2 5 ma 2, 3 cmos standby current (ce=v cc 0.2v, ce2=gnd+0.2v) i cc3 1 3 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v output voltage v cco1 v cc 0.3 v 4 output current i cco1 85 ma 4 write protection voltage v pf 4.0 4.25 4.5 v 5 output voltage v cco2 v bat 0.3 v 6 output current i cco2 100 m a 6 battery leakage osc on i bat1 500 na battery leakage osc off i bat2 100 na switch over voltage v so v bat1 , v bat2 v
DS1384 062598 10/15 ac electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min type max units notes read cycle time t rc 120 ns address access time t acc 120 ns ce access time t co 120 ns ce data off time t cez 40 ns output enable access time t oe 60 ns output enable data off time t oez 40 ns output enable to dq low-z t oel 5 ns ce to dq low-z t cel 10 ns output hold from address t oh 5 ns ce to ceo low or high t cepd 25 ns oe low to oer low a0a16 > 00040h t oerl 20 ns oe high to oer high time t ro 20 ns address 00040h1ffffh to oer low t aoel 50 ns address 00000h0003fh to oer high t aoeh 40 ns write cycle time t wc 120 ns address setup time t aw 0 ns ce pulse width t cew 120 ns address hold from end of write t ah 10 ns write pulse width t wp 80 ns ce data off time t cez 40 ns we data off time t wez 40 ns we or ce inactive time t wr 10 ns data setup time t ds 45 ns data hold time high t dh 0 ns inta and intb pulse width t ipw 3 ms ac test conditions input levels: 0v to 3v transition times: 5 ns
DS1384 062598 11/15 capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all pins (except dq) c i 7 15 pf capacitance on dq pins c dq 7 15 pf ac electrical characteristics (power-up/down timing) (0 c to 70 c) parameter symbol min typ max units notes ce at v ih before power down t pd 0 m s v pf (max) to v pf (min) v cc fall time t f 300 m s v pf (min) to v so v cc fall time t fb 10 m s v pf (min) to v pf (max) v cc rise time t r 0 m s power up t rec 10 150 ms expected data retention time (oscillator on) t dr 10 years 7 read cycle timing: rtc and external sram control signals t rc t rc t rc read read write t ah t aw t wr t wp valid in valid out valid out t oez t acc t oh t co t cel t oe t oel a0a16 ce oe we dq0dq7 oer * ceo t cepd t ro * see the following timing diagram for more specifics on oer timing.
DS1384 062598 12/15 oer timing when switching between lower memory (00000h0003fh) and upper memory (00040h1ffffh) oe oer ce 00000h 0003fh 00040h 1ffffh 00000h 0003fh 00040h 1ffffh t aoel t aoeh t oerl t ro a0a16 write cycle timing: rtc and external sram control signals t wc t wc t wc write write read a0a16 ce oe we dq0 valid out valid in valid in valid out t acc t ah t oe t wez t aw t cew t cez t ds t dh t dh t ds dq7 t wr ceo t cepd t cepd oer t ro t wp t wr
DS1384 062598 13/15 timing diagram: power up t cepd v bat - 0.2v t r v pf (min) v pf (max) ce cer pfo v cci t rec timing diagram: power down v bat - 0.2v v pf (min) v pf (max) ce cer pfo v cci t cepd v so t fb t f t pd
DS1384 062598 14/15 timing diagram: interrupt outputs pulse mode (see notes 8, 9) intb inta , intb t ipw notes: 1. all voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. value for voltage and currents is from the v cci input pin to the v cco pin. 5. write protection trip point occurs during power fail prior to switchover from v cc to v bat . 6. value for voltage and currents is from the v bat input pin to the v cco pin. 7. data retention time depends on the size of battery selected and the amount of current demanded by the static ram in back-up mode. the battery capacity (ma ? hr) to achieve a t dr of 10 years is given by the formula: c=(i bat1 + i ram ) x 24 x 365 x 10, where i ram is the standby current of the static ram at the battery voltage. for the DS1384 chip alone, a standard 48 mah lithium cell battery will provide greater than 10 years of data retention in the absence of power. 8. applies to both interrupt pins when the alarms are set to pulse. 9. interrupt output occurs within 100 ns of the alarm condition existing. output load +5 volts 50 pf d.u.t. 1.8 k w 1 k w
note: 1. dimensions d1 and e1 include mold mismatch, but do not include mold protrusion; allowable protrusion is 0.25 mm per side. 2. details of pin 1 identifier are optional but must be located within the zone indicated. 3. allowable damper protrusion is 0.08 mm total in excess of the b dimension; at maximum material condition. protrusion not to be located on lower radius of foot of lead. 4. controlling dimensions: millimeters. 56g3001001, 56g4012001 DS1384 062598 15/15 DS1384 fp package outlines pkg DS1384fp dim min max a 2.45 a1 0.10 0.30 a2 1.95 2.10 d 13.65 14.30 d1 9.90 10.00 e 13.65 14.30 e1 9.90 10.00 l 0.63 1.03 e 0.80 bsc b 0.30 0.45 c 0.13 0.23

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